The present invention relates generally to bipolar integrated circuits and more particularly to integrated injection logic (I.sup.2 L).
The use of merged transistor logic or integrated injection logic (I.sup.2 L) has made possible high packing density of low power integrated circuits. The standard I.sup.2 L structure is an NPN device with an active PNP load fabricated such that the collector of the PNP and the base of the NPN share the same semiconductor region and the base of the PNP and the emitter of the NPN are common. The structures of the prior art have generally not provided both transistors having a high gain or Beta. Similarly, the particular structure and method of fabrication of I.sup.2 L structure of the prior art have not permitted their effective use with transistor to transistor logic (T.sup.2 L). Thus three exists a need for an I.sup.2 L structure which is simple to manufacture and provides complementary transistors sboth with high current gains and in an integrated circuit which allows compatibility with T.sup.2 L devices.